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LR38637
LR38637
DESCRIPTION
The LR38637 is a CMOS digital signal processor for color digital video camera systems of 110 kpixel (CIF)/350 k-pixel (VGA) CMOS image sensors with primary color mosaic filters.
Digital Signal Processor For VGA/CIF CMOS Image Sensors
* Supported CMOS image sensors - Image size : 110 k pixels (CIF)/350 k pixels (VGA) - R, G and B primary color mosaic filters : Bayer matrix, 10 bits per color * Built-in synchronous signal generation circuit for CMOS image sensors * Built-in parallel digital output function - 16-bit outputs : YUV, RGB format - 8-bit outputs : UYVY format * Output image sizes for VGA CMOS image sensors : VGA, QVGA, QQVGA, CIF, QCIF, QQCIF * Output image sizes for CIF CMOS image sensors : QVGA, QQVGA, CIF, QCIF, QQCIF * Used for video cameras by combining with CMOS image sensor * Parameters required for image signal processing can be changed * Built-in auto exposure control * Built-in auto carrier balance control * Built-in auto white balance control * Built-in drive circuit for 2k-bit EEPROM * Built-in auto white detect correction * Built-in shading correction control * Power supplies - +2.5 V10% for internal digital circuits - +2.7 to +3.6 V for digital circuits * Package : 100-pin LQFP (P-LQFP100-1414) 0.5 mm pin-pitch
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In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs, data books, etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device.
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1
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FEATURES
LR38637
PIN CONNECTIONS
100-PIN LQFP TOP VIEW
100 NC 99 NC 98 NC 97 NC 96 NC 95 DVDD2 94 MODE1 93 TEST4Z 92 TEST3Z 91 TEST2Z 90 TEST1Z 89 DGNG 88 RCLK2 87 VS 86 DVDD 85 HREF 84 RCLK 83 DVDD2 82 EXTCLK 81 CKI 80 CKO 79 DGND 78 UV7 77 UV6 76 UV5
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CHD 26 CVD 27 SCKO 28 CSTDBYO 29 DGND 30 SCKI 31 AD0 32 AD1 33 AD2 34 AD3 35 DVDD 36 AD4 37 AD5 38 AD6 39 AD7 40 AD8 41 AD9 42 DVDD2 43 DVDD 44 DGND 45 NC 46 NC 47 NC 48 NC 49 NC 50
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DGND 1 TEST5Z 2 TEST6Z 3 TEST7Z 4 TEST8Z 5 TEST9Z 6 DVDD 7 DGND 8 STDBY 9 SDA 10 SDC 11 DVDD2 12 DVDD 13 DVDD2 14 DAS 15 EEPINIT 16 MITYPE 17 SDI 18 SCLK 19 SLOAD 20 NC 21 NC 22 NC 23 NC 24 NC 25
75 NC 74 NC 73 NC 72 NC 71 NC 70 UV4 69 UV3 68 UV2 67 UV1 66 UV0 65 DGND 64 Y7 63 DVDD 62 Y6 61 Y5 60 Y4 59 Y3 58 Y2 57 Y1 56 Y0 55 IOCTRL 54 ADJ 53 LP 52 ACL 51 DGND
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(P-LQFP100-1414)
IN
2
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Y
LR38637
BLOCK DIAGRAM
AD9-AD0 TEST1Z TEST2Z TEST3Z TEST4Z IOCTRL SDI SCLK SLOAD
OB CLAMP CARRIER BALANCE
SHADING CORRECTION
WHITE BALANCE
GAMMA CORRECTION
1H, 2H DELAY AUTO WHITE DETECT CORRECTION
INTERPOLATION
AUTO WHITE BALANCE IRIS PROCESSING ILLUMINATION SIGNAL TO INTERNAL REGISTER
SCKI CHD CVD SCKO CSTDBYO Y7-Y0 UV7-UV0 RCLK RCLK2 VS HREF SDA SDC DAS EEPINIT MITYPE EXTCLK STDBY LP ADJ MODE1 CKI CKO
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DSP SERIAL I/F
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TEST5Z TEST6Z TEST7Z TEST8Z TEST9Z
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IN
CLOCK CONTROL MODULE
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SENSOR DRIVER
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CONVERSION OF OUTPUT FORMAT
Y
PROCESSING COLOR SIGNAL
LR38637
PIN DESCRIPTION
PIN NO. SYMBOL 1 DGND 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 TEST5Z TEST6Z TEST7Z TEST8Z TEST9Z DVDD DGND STDBY SDA SDC DVDD2 DVDD DVDD2 DAS EEPINIT MITYPE SDI SCLK SLOAD NC NC NC NC NC CHD CVD SCKO IO SYMBOL - Ground - - - - - - - IL IOL4 IOL4 - - - I I I O4 O4 O4 - - - - - DESCRIPTION
Test input (Must be open.) (NOTE 4) Test input (Must be open.) (NOTE 4) Test input (Must be open.) (NOTE 4) Test input (Must be open.) (NOTE 4) Test input (Must be open.) (NOTE 4) Internal power supply (+2.5 V) Standby mode control Low level input : The LR38637 and CMOS image sensor are in normal mode. High level input : The LR38637 and CMOS image sensor are in standby mode. DSP serial data input/output (NOTE 5, 6) DSP serial clock input/output (NOTE 5, 6) I/O power supply (+3.0 V) Internal power supply (+2.5 V)
Control of auto reading from EEPROM. Low level input : The LR38637 does NOT read automatically from EEPROM. High level input : The LR38637 reads automatically from EEPROM. Connect to High level (+3.0 V). Serial data output for CMOS image sensor Serial clock output for CMOS image sensor Serial load output for CMOS image sensor Must be open. Must be open. Must be open. Must be open. Must be open.
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CSTDBYO
DGND SCKI AD0 AD1 AD2 AD3
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O4 O4 O4
O12 - I I I I I
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Horizontal drive pulse output for CMOS image sensor Vertical drive pulse output for CMOS image sensor Clock output for CMOS image sensor Standby control output to CMOS image sensor Low level output : CMOS image sensor is in normal mode. High level output : CMOS image sensor is in standby mode. Ground Clock input from CMOS image sensor Digital input bit 0 Digital input bit 1 Digital input bit 2 Digital input bit 3
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I/O power supply (+3.0 V) DSP DAS device address input
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Ground
LR38637
PIN NO. SYMBOL 36 DVDD 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 AD4 AD5 AD6 AD7 AD8 AD9 DVDD2 DVDD DGND NC NC NC NC NC DGND ACL
IO SYMBOL DESCRIPTION - Internal power supply (+2.5 V) I I I I I I - - - - - - - - - IS Digital input bit 4 Digital input bit 5 Digital input bit 6 Digital input bit 7 Digital input bit 8 Digital input bit 9 Internal power supply (+2.5 V) Ground Must be open. Must be open. Must be open. Must be open. Must be open. Ground Reset input (low active)
Lower power mode control 53 LP I
Low level input : The LR38637 and CMOS image sensor are in normal mode. High level input : The LR38637 and CMOS image sensor are in low power mode. Connect to Low level (+0.0 V) Switch input/output of parallel video output. (NOTE 7) Digital video output (NOTE 8) Digital video output (NOTE 8) Digital video output (NOTE 8) Digital video output (NOTE 8) Digital video output (NOTE 8) Digital video output (NOTE 8)
54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73
ADJ IOCTRL Y0 Y1 Y2 Y3 Y4 Y5 Y6 DVDD Y7
I I IO4 IO4 IO4 IO4 IO4 IO4 IO4 - IO4 - IO4 IO4 IO4 IO4 IO4 - - -
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DGND UV0 UV1 UV2 UV3 UV4 NC NC NC
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Digital video output (NOTE 8) Internal power supply (+2.5 V)
Digital video output (NOTE 8) Ground Digital video output (NOTE 8) Digital video output (NOTE 8) Digital video output (NOTE 8) Digital video output (NOTE 8) Digital video output (NOTE 8) Must be open. Must be open. Must be open.
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I/O power supply (+3.0 V)
LR38637
PIN NO. SYMBOL 74 NC 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
I IL IS IU O4 O12 : : : : : :
IO SYMBOL - Must be open. - IO4 IO4 IO4 - OSC IA IAC - O4 O4 - O4 O4 - IU IU IU IU I - - - - - - Must be open. Digital video output. (NOTE 8) Digital video output. (NOTE 8) Digital video output. (NOTE 8) Ground System clock oscillator output
DESCRIPTION
NC UV5 UV6 UV7 DGND CKO CKI EXTCLK DVDD2 RCLK HREF DVDD VS RCLK2 DGND TEST1Z TEST2Z TEST3Z TEST4Z MODE1 DVDD2 NC NC NC NC NC
Connect to High level (+3.0 V) . I/O power supply (+3.0 V) Clock output synchronized with digital video output Horizontal blank pulse of digital video output Internal power supply (+2.5 V) Vertical blank pulse of digital video output Separated video output Test input (Must be open.) (NOTE 3) Test input (Must be open.) (NOTE 3) Test input (Must be open.) (NOTE 3) Test input (Must be open.) (NOTE 3) Connect to Low level (+0.0 V). I/O power supply (+3.0 V) Must be open. Must be open. Must be open.
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Must be open. Must be open.
IO4 : IOL4 : IA : OSC : IAC : Input/output pin Schmidt input/output pin (Nch open drain) Input pin for oscillation Output pin for oscillation Input pin for external clock
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Input pin Input pin Schmidt input pin Input pin with pull-up resistor Output pin Output pin
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6
IN
Ground
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Y
System clock oscillator input
LR38637
REMARKS :
PIN TYPE (MAX. OUTPUT CURRENT) +3.0 V output pin (10 m A) +3.0 V I/O pin (3 mA) or output pin (3 mA) APPLICABLE PINS CSTDBYO SDA, SDC, SDI, SCLK, SLOAD, CHD, CVD, SCKO, Y0 to Y7, UV0 to UV7, RCLK, HREF, VS, RCLK2
5. SDA and SDC are input pins at resetting (ACL is Low level). 6. SDA and SDC are N-ch open-drain outputs, so use them with external pulled-up resistor. 7. When an IOCTRL pin is at High condition, the image output pins (Y0 to Y7, UV0 to UV7) are input pins. 8. The output form of the image output pins (Y0 to Y7, UV0 to UV7) can be changed by parameter setting.
NOTES :
1. Be careful that an input pin doesn't have a floating potential. 2. Be careful not to have a floating potential when an I/O pin is set to input. 3. Keep test pins TEST1Z to TEST4Z normally open or "High level". 4. Keep test pins TEST5Z to TEST9Z normally open.
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LR38637
FUNCTIONAL DESCRIPTION Oscillation Circuit
Oscillation circuit leads the same frequency of the
quartz crystal connected to I/O pins and provides the same frequency to the internal logic circuits as shown in Fig. 1 and Fig. 2.
CKI Oscillation Circuit (I/O Buffer) CKO To Internal Logic
C1
RD2 C2 RD1
IN
C1 [pF] 10
Fig. 2 Clock Input to Oscillation Circuit
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Connection of Quartz Crystal (TA = -20 to +70C, DVDD2 = 2.7 to 3.6 V, DVDD = 2.25 to 2.75 V) : Example of Oscillation under Fundamental Frequencies APPLICABLE PINS CKI, CKO FUNDAMENTAL FREQUENCY [MHz] 24.5454 or 9.0000 RECOMMENDED COEFFICIENT C2 [pF] RD1 [$] 10 220 RD2 [$] 1M
NOTES :
Clock
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1. The oscillation circuit should be located as close to CKI, CKO as possible. 2. Do not install other signal lines in the shaded area. 3. Perform due evaluation on the match between the LR38637 and the quartz crystal.
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Power ON/OFF Sequence
Two power supplies are used with the LR38637. One (DVDD2) is used for I/O buffer and the other (DVDD) is used for the core logic circuits. Power ON : Be sure to turn ON the internal power of DVDD first. Power OFF : Be sure to turn OFF the I/O buffer of DVDD2 first.
Input clock from the CKI pin is supplied to CMOS image sensor through the SCKO pin after dividing according to inside parameter of the LR38637. Set the EXTCLK pin to open or "High level". The clock frequency which can be inputted to the CKI input pin is 24.5454 MHz or 9 MHz.
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CKI CKO
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Fig. 1 Block Diagram of Oscillation Circuit
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LR38637
ABSOLUTE MAXIMUM RATINGS
PARAMETER I/O power supply voltage Internal power supply voltage Input voltage Output voltage Storage temperature SYMBOL DVDD2 DVDD VI2 VO2 TSTG RATING -0.3 to +4.3 -0.3 to +3.3 -0.3 to DVDD2 + 0.3 -0.3 to DVDD2 + 0.3 -65 to +150 UNIT V V V V C
RECOMMENDED OPERATING CONDITIONS
Power supply voltage Operating temperature Operating frequency
fOPR
Internal logic
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12.27 TYP. -30 24.5454
DVDD TOPR
Internal digital power supply
2.25 -20
2.50 +25
ELECTRICAL CHARACTERISTICS DC Characteristics
PARAMETER Input "Low" voltage 1 Input "High" voltage 1 Input "Low" voltage 2 Input "High" voltage 2 Positive trigger voltage Negative trigger voltage Hysteresis voltage Hysteresis voltage Input leakage current Input "Low" current SYMBOL VIL1 VIH1 VIL2 VIH2 VT+ VT+ VT-
CONDITIONS
IN
9
(DVDD2 = 3.0 V, DVDD = 2.5 V, TA = -20 to +70C)
MIN. MAX. UNIT 0.3DVDD2 V 0.2DVDD2 V V V V 1.21 0.17 0.1DVDD2 -1.0 -5.0 +1.0 +5.0 V V V A A A 0.2DVDD2 0.5 DVDD2 - 0.5 0.5 DVDD2 - 0.5 V V V V V MHz 7 8 9 10 NOTE 1 2
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0.7DVDD2 0.8DVDD2 1.24
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2.75 +70
PARAMETER
SYMBOL DVDD2
CONDITIONS I/O digital power supply
MIN. 2.7
TYP. 3.0
MAX. 3.6
UNIT V V C
MHz
3 4 5 6
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II2 IIL VOL1 VOL2 VOH2 VOL3 VOH3 FOSC
- VHYS
VT-
VIN = 0V to DVDD2 VIN = DVDD2 [with pull-up 98 k$] VIN = 0 V IOL = 3 mA IOL = 3 mA IOH = -3 mA IOL = 10 mA IOH = -7 mA
Output "Low" voltage 2 Output "High" voltage 2
Oscillation frequency
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Output "Low" voltage 3 Output "High" voltage 3
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Output "Low" voltage 1
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LR38637
(DVDD2 = 3.0 V, DVDD = 2.5 V, TA = 25C)
PARAMETER SYMBOL CONDITIONS Input : VGA sensor Output : 15 fps, parallel output * This value is reference value with our evaluation environment. Standby current PSB * This value is reference value with our evaluation environment. TBD A 12 MIN. TYP. MAX. UNIT NOTE
Supply current
IDD
TBD
mA
11
NOTES :
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. Applicable to IO symbols IL, IOL4. Applicable to IO symbol I, IU, IO4. Applicable to IO symbol IS. Applicable to IO symbol IOL4. Applicable to IO symbols I, IO4, IS, IL, IOL4. Applicable to IO symbol IU. Applicable to IO symbol IOL4. Applicable to IO symbols O4, IO4. Applicable to IO symbol O12. Applicable to IO symbols IA (CKI), OSC (CKO). Test conditions Connected 8-bit CMOS image sensor : VGA image sensor/VGA mode External clock : MODE1 = "Low", EXTCLK = "High", CKI = 24.5454 MHz Output frame rate : CLK_MODE = "001" (15 frames/s) Parallel output : Operation (IOCTRL = "Low", Y0 to Y7, UV0 to UV7 = "Open" Output format : YUV (OUT_SEL = "00") Output frame size : VGA (640 x 480)
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12. Test conditions STDBY, EXTCLK, SDA, SDC, MODE1 = "High", CKI, IOCTRL, DAS, EEPINIT, MITYPE, SCKI, AD0 to AD9, ACL, LP, ADJ = "Low", CKO, Y0 to Y7, UV0 to UV7, TEST1Z to TEST9Z, SDI, SCLK, SLOAD, CHD, CVD, SCKO, CSTDBYO, RCLK, HREF, VS, RCLK2 = "Open"
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LR38637
AC Characteristics
CMOS IMAGE SENSOR INTERFACE TIMING
CKI TCVDD
CVD TCHDD
CHD TCKOD SCKO TSDID
TSCLKD SCLK TSLOADD
SLOAD
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SYMBOL TCVDD TCHDD TSCKOD TSDID TSCLKD TSLOADD TADS TADH 10 10 CONDITIONS MIN. MAX. 15 15 15 15 15 15 ns ns ns ns ns ns ns ns
IN
TADS TADH
SDI
AD9-AD0
Fig. 3 CMOS Image Sensor Interface Timing
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(DVDD2 = 3.0 V, DVDD = 2.5 V, TA = -20 to +70C)
UNIT NOTE 1 1 1 1 1 1 1 1
PARAMETER
SCKO output delay SDI output delay SCLK output delay SLOAD output delay Setup time of AD9-AD0 input data Hold time of AD9-AD0 input data
NOTE :
1. Output load capacitance CL = 15 pF
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CVD output delay CHD output delay
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LR38637
DIGITAL PARALLEL OUTPUT TIMING
RCLK TVSD
VS THREFD
HREF TRCLK2D RCLK2 TYD
Y7-Y0 TUVD UV7-UV0
Fig. 4 Digital Parallel Output Timing
(DVDD2 = 3.0 V, DVDD = 2.5 V, TA = -20 to +70C)
PARAMETER VS output delay HREF output delay RCLK2 output delay Y7 to Y0 output delay SYMBOL TVSD THREFD CONDITIONS MIN. -15 -15 -15 -15 -15 MAX. +15 +15 +15 +15 +15 UNIT ns ns ns ns ns NOTE 1 1 1 1 1
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NOTE :
1. Output load capacitance CL = 15 pF
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UV7 to UV0 output delay
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TRCLK2D TYD TUVS
IN
12
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LR38637
DSP SERIAL INTERFACE TIMING
VIN 0.7DVDD2 0.3DVDD2 VOUT 0.8DVDD2 VOUT 0.9DVDD2
0.2DVDD2 TF
0.1DVDD2
HOST I/F TIMING
TIC TICL SDC In TISS SDA In TIHS TISD TICH
TIHD
A
NOTE kHz s s s s s s s s s s 1 1 ns 1
SDA
Out
(DVDD2 = 3.0 V, DVDD = 2.5 V, TA = -20 to +70C)
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PARAMETER
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SYMBOL TIC TICH TICL TISS TIHS TISD TIHD TOAA TODH TISP TIHP TF 0.1 0.2 0.1 0.1 0.1 0 0 0 0.1 0.1 MIN.
Fig. 6 Host I/F Timing
CONDITIONS MAX. 400
Operating clock frequency High clock period
Low clock period Setup time of start condition
Hold time of input data Output delay Hold time of output data Setup time of stop condition Hold time of stop condition Falling period
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Hold time of start condition Setup time of input data
R
NOTE :
1. Output load capacitance CL = 15 pF
IN
TOAA TODH
UNIT
300
13
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TISP TIHP
Y
Fig. 5 I/O Level and Rising Time
LR38637
EEPROM I/F TIMING
TOO TOC TOCL SDC Out TOS SDA Out TOAA TOP TOCH TOO
TISD SDA In
TIHD
Fig. 7 EEPROM I/F Timing
(DVDD2 = 3.0 V, DVDD = 2.5 V, TA = -20 to +70C)
MIN. 0 8.78 8.78
Operating clock frequency High clock period Low clock period Start condition output delay Setup time of input data Hold time of input data Output delay Stop condition output delay SDC bus release time
TOC TOCH TOCL TOS TISD
IN
MAX. 56.93 kHz s s s s s s s s
PARAMETER
SYMBOL
CONDITIONS
UNIT
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17.56 1 0 4.39 26.34 70.24 TIHD
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TOAA TOP TOO
1. Output load capacitance CL = 15 pF 2. Available maximum clock frequency is 24.5454 MHZ (CKI).
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NOTES :
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NOTE 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2
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LR38637
PACKAGE OUTLINES 100 LQFP (P-LQFP100-1414)
P-0.5TYP. 75 76 100-0.20.08 51 50 0.08 (1.0) M 0.1250.05 See Detail A
(Unit : mm)
14.00.2
16.00.3
100 1 (1.0) 14.00.2 16.00.3
26 (1.0) Detail A 0.64 1.40.2 0.125 0.64 1.70MAX. 0.10.1 1.40.2 Package base plane 0-10 0.10.1 0.25 1.00.15
25 (1.0)
0.10
Seating plane
0.60.15
15

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